Storage arrays within integrated-circuit memory components are typically accessed in two phases. First, an address-specified page of data is transferred from a row of storage cells to a bank of sense amplifiers in a row activation operation. Thereafter, one or more column read or write operations are executed to access address-specified columns of the page of data within the sense amplifier bank, reading or writing column data within the open page.
Row activation tends to be particularly time consuming, as signals representative of data within individual storage cells are sensed via long, high-capacitance bit lines. To mitigate this timing bottleneck, memory cores have traditionally been architected with relatively high number of columns per row to increase the likelihood that a sequence of memory access requests will “hit” the same open page (i.e., exploiting spatial/temporal locality), and thus enable multiple relatively low-latency column operations per row activation. Unfortunately, the power expended to activate a given storage row is largely wasted as the vast majority of the data transferred to the sense amplifiers during row activation remains untouched in ensuing column operations.